CY2XP304 module equivalent, high-frequency programmable pecl clock generation module.
* Period jitter peak-peak 125MHz(max.) = 55 ps
* Four low-skew LVPECL outputs
* Phase-locked loop (PLL) multiplier select
* Serially-configurable multiply.
* High-speed PLL bypass mode to 1.5 GHz
* 36-VFBGA, 6 × 8 × 1 mm
* 3.3V operation
Block Diagram
PLL_MULT CL.
3.3V Power Supply for Crystal Driver
SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down. HIGH .
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